1. Field of the Invention
The invention relates to integrated circuits, and more particularly to reference voltage or current generators.
2. Discussion of the Related Art
Many integrated circuits now work in a normal mode and in a standby mode with reduced consumption. This standby mode is implemented when the circuit does not need to perform all the normal functions for which it is designed. All that the circuit does then is to watch for the appearance of an event that should reactivate the normal functions. In this standby mode, it is desirable that the normal functions should not consume current unnecessarily.
This is why it is now common practice to disconnect a certain number of circuit arms that might consume current unnecessarily in standby mode. The standby mode is defined by a determined logic state, 0 or 1, of a logic signal present at an internal node or at an external access terminal of the circuit. This logic signal is used to control switches that cut off the current consumption in the different arms of the integrated circuit.
As in the case of the other functions of the integrated circuit, it is appropriate to cut off the current consumption of reference voltage or current generators, in the integrated circuit, when in standby mode. These generators are the circuit elements that give the stable levels of voltage or current needed for the operation of the other elements of the integrated circuit. However, it is generally necessary that these generators should restart very swiftly and in a controlled way (especially without oscillation) when the circuit goes back into normal operation mode. It is indeed indispensable that these generators should not give uncontrolled random states during the time when the normal mode is being restored.
In the same way, these reference voltage generators should not give uncontrolled levels during the stages when the integrated circuit is subjected to power-on reset operations, i.e. when the circuit is powered again after its supply has been cut off.
A system has been devised where the current consumption in these reference generators is controlled by a logic signal that may be called "POR-STBY". When this signal is at 1, the system is in standby mode. When it is at 0, the system is in normal mode. And furthermore this signal undergoes a transition from 1 to 0, set up by a power-on-reset circuit when the supply voltage of the integrated circuit returns to a sufficient level after a brief or long-lasting cut.
A reference voltage (or reference current) generator, in CMOS technology, conventionally has at least one current circulation arm in which there are an N channel transistor and a P channel transistor in series, one of the two transistors having its gate connected to its drain. In general, there are at least two arms of this type, and the two arms are coupled so as to set up mutual copies of current which are the basis of the structure of such reference generators.
FIG. 1 shows a typical example of a reference generator comprising four transistors, P1, P2 (P channel transistors) and N1, N2 (N channel transistors). The P channel transistors have their gates joined together and their sources connected to a supply terminal A at a potential Vdd. The N channel transistors have their gates connected together and their sources connected to a ground terminal B. The drains of P1 and N1 are connected to form a first current arm. The drains of P2 and N2 are connected to form a second current arm. The gate of P1 is connected to its drain and forms a first output S1 giving a first reference voltage VrefP. The gate of N2 is connected to its drain and forms a second output S2 giving a second reference voltage VrefN.
The circuit of FIG. 1 is therefore a double generator of reference voltages. It is used when it is desired to produce two reference voltages close to the threshold voltages of the N and P transistors respectively of the integrated circuit. There are many other examples of generators giving one or more reference voltages.
FIG. 2 shows a proposal already made for cutting off the consumption of the reference generator of FIG. 1 in standby mode and for restarting on the trailing edge of the logic signal POR-STBY. This trailing edge appears after a standby or after an operation to restore the supply voltage Vdd.
This proposal entails:
inserting two transistors Q1 and Q2 respectively in the arm P1, N1 and in the arm P2, N2, these transistors being off in standby mode and conductive in normal mode. For example, they are P channel transistors inserted between the transistors P1, P2 and the terminal A at Vdd and controlled by the signal POR-STBY, or else they are N channel transistors inserted between N1, N2 and the ground and controlled by the signal NPOR-STBY which is the logic complement of the control signal POR-STBY generated by inverter INV;
using a low threshold voltage transistor D1 to short-circuit the two reference outputs S1 and S2 to give them an intermediate common potential during the standby;
and placing a capacitor C between the input POR-STBY and the gates of transistors P1 and P2, or between the control signal NPOR-STBY and the gates of transistors N1 and N2.
The transistors Q1 and Q2 cut off the consumption. The transistor D1 makes it possible for the outputs S1 and S2 to start from one and the same mean level at the time of a power-on-reset or restarting operation. The capacitor C makes it possible to heavily unbalance the circuit at the time of the power-on-reset operation (on the trailing edge of POR-STBY) to prevent the reference generator from recovering its normal state far too slowly, especially when the transistors that form it are highly resistive, which is often the case.
It has been observed that one drawback of this circuit is the fact that the output nodes S1 and S2 are at floating potentials in standby mode. If this potential were to be truly in the middle of the interval between the levels VrefN and VrefP, this could be acceptable. But, this is not certain. Furthermore, the capacitor C takes up a great deal of space on the integrated circuit. Finally, this circuit works on condition that the supply voltage Vdd present at the time of the trailing edge POR-STBY is high enough. Now, it is increasingly sought to have circuits that work even at very low supply voltages, especially circuits for which the power-on-reset operation is ensured for a small level of Vdd (about 2 volts approximately) after cut-off.